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MITSUBISHI
M66258FP
8192 x 8-BIT LINE MEMORY
DESCRIPTION
The M66258FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 8192 words x 8 bits. The M66258FP, performing reading and writing operations at different cycles independently and asynchronously, is optimal for buffer memory to be used between equipment of different data processing speeds.
PIN CONFIGURATION (TOP VIEW)
Q0 Q1 DATA OUTPUT Q2 Q3 READ ENABLE RE INPUT READ RESET RRES INPUT GND READ CLOCK INPUT RCK Q4 DATA OUTPUT
1 2 3 4 5 6 7 8 9
24 D0 23 D1 22 D2 21 D3 WRITE ENABLE INPUT 19 WRES WRITE RESET INPUT 20 WE 18 VCC 17 WCK 16 D4 15 D5 DATA INPUT 14 D6 13 D7 WRITE CLOCK INPUT DATA INPUT
FEATURES
* * * * * Memory configuration 8192 words x 8 bits configuration High speed cycle 20 ns (Min.) High speed access 16 ns (Max.) Output hold 3 ns (Min.) Reading and writing operations can be completely carried out independently and asynchronously. * Variable length delay bit * Input/output TTL direct connection allowable * Output 3 states
M66258FP
Q5 10 Q6 11 Q7 12
APPLICATION
* Digital copying machine, laser beam printer, high speed facsimile, etc.
Outline 24P2U-A(SSOP)
FUNCTIONAL DESCRIPTION
When write enable input WE is set to "L", the contents of data inputs D0 to D7 are read in synchronization with a rising edge of write lock input WCK to perform writing operation. When this is the case,the write address counter is also incremented simultaneously. When WE is set to "H", the writing operation is inhibited and the write address counter stops. When write reset input WRES is set to "L", the write address counter is initialized. When read enable input RE is set to "L", the contents of memory are output to data outputs Q0 to Q7 in synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the read address counter is incremented simultaneously. When RE is set to "H", the reading operation is inhibited and the read address counter stops. The outputs are placed in a high impedance state. When read reset input RRES is set to "L", the read address counter is initialized.
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2 Data inputs D0 to D7 Data outputs Q0 to Q7 15 16 21 22 23 24 1 2 3 4 9 10 11 12 Input buffer Output buffer 5 RE Read enable input 6 RRES Read reset input Read control circuit Read address counter Write address counter Memory array 8192 x 8 bits 8 RCK Read clock input 7 GND
BLOCK DIAGRAM
13
14
Write enable input
WE 20
Write control circuit
Write reset input WRES 19
Write clock input
WCK 17
VCC 18
M66258FP
MITSUBISHI
8192 x 8-BIT LINE MEMORY
MITSUBISHI
M66258FP
8192 x 8-BIT LINE MEMORY ABSOLUTE MAXIMUM RATINGS (Ta=0 - 70 C unless otherwise noted)
Symbol Vcc VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Power dispersion Storage temperature Conditions Ratings -0.5 - +6.0 -0.5 - VCC+0.5 -0.5 - VCC+0.5 825 -65 - 150 Unit V V V mW C
Value based on the GND pin Ta=25 C
RECOMMENDED OPERATING CONDITIONS
Symbol Vcc GND Topr Parameter Supply voltage Supply voltage Operating temperature Min. 4.5 Limits Typ. 5.0 0 0 - 70 Max. 5.5 Unit V V C
ELECTRICAL CHARACTERISTICS (Ta=0 - 70 C, Vcc=5V10%, GND=0V unless otherwise noted)
Symbol VIH VIL VOH VOL IIH Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input current Conditions Min. 2.0 VCC-0.8 0.55 WE, WRES, WCK, RE, RRES, RCK, D0 - D7 WE, WRES, WCK, RE, RRES, RCK, D0 - D7 1.0 Limits Typ. Max. 0.8 IOH = -4mA IOL = 4mA VI = VCC Unit V V V V
A
IIL IOZH IOZL ICC CI CO
Low-level input current Off-state high-level output current Off-state low-level output current Average supply current during operation Input capacitance Off-time output capacitance
VI = GND VO = VCC VO = GND
-1.0 5.0 -5.0 150 10 15
A A A
mA pF pF
VI = VCC, GND, output open tWCK, tRCK = 20ns f = 1MHz f = 1MHz
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MITSUBISHI
M66258FP
8192 x 8-BIT LINE MEMORY SWITCHING CHARACTERISTICS (Ta=0 - 70 C, Vcc=5V10%, GND=0V unless otherwise noted)
Symbol tAC tOH tOEN tODIS Access time Output hold time Output enable time Output disable time Parameter Min. 3 3 3 Limits Typ. Max. 16 16 16 Unit ns ns ns ns
TIMING REQUIREMENTS (Ta=0 - 70 C, Vcc=5V10%, GND=0V unless otherwise noted)
Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH tr, tf tH Parameter Write clock (WCK) cycle Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) "L" pulse width Input data set up time for WCK Input data hold time for WCK Reset set up time for WCK/RCK Reset hold time for WCK/RCK Reset non-selection set up time for WCK/RCK Reset non-selection hold time for WCK/RCK WE set up time for WCK WE hold time for WCK WE non-selection set up time for WCK WE non-selection hold time for WCK RE set up time for RCK RE hold time for RCK RE non-selection set up time for RCK RE non-selection hold time for RCK Input pulse up/down time Data hold time (Note 1) Min. 20 8 8 20 8 8 4 3 4 3 4 3 4 3 4 3 4 3 4 3 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
20 20
Note 1: For 1 line access, the following conditions must be satisfied: WE high-level period 20 ms - 8192 * tWCK - WRES low-level period RE high-level period 20 ms - 8192 * tRCK - RRES low-level period 2: Perform reset operation after turning on power supply.
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MITSUBISHI
M66258FP
8192 x 8-BIT LINE MEMORY
SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT
VCC
RL=1K SW1
Qn
Qn
SW2 CL = 30pF : tAC, tOH RL=1K CL = 5pF : tOEN, tODIS
Input pulse level Input pulse up/down time Judging voltage Input Output
: 0 - 3V : 3 ns : 1.3V : 1.3V(However, tODIS(LZ) is judged with 10% of the output amplitude, while tODIS(HZ) is judged with 90% of the output amplitude.) Load capacitance CL includes the floating capacity of connected lines and input capacitance of probe.
Item tODIS(LZ) tODIS(HZ) tOEN(ZL) tOEN(ZH)
SW1 Close Open Close Open
SW2 Open Close Open Close
tODIS and tOEN measurement condition
3V RCK 1.3V 1.3V GND
3V RE GND tODIS(HZ) tOEN(ZH)
Qn
90% 1.3V tOEN(ZL) tODIS(LZ) 1.3V 10%
VOH
Qn
VOL
5
MITSUBISHI
M66258FP
8192 x 8-BIT LINE MEMORY
OPERATION TIMING
* Write cycle
n cycle
n+1 cycle
n+2 cycle
Disable cycle
n+3 cycle
n+4 cycle
WCK tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WE tDS tDH
Dn
(n)
(n+1)
(n+2)
(n+3)
(n+4)
WRES = "H"
* Write reset cycle
n-1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
2 cycle
WCK tWCK tNRESH tRESS tRESH tNRESS
WRES
tDS tDH
Dn
(n-1)
(n)
(0)
(1)
(2)
WE = "L"
6
MITSUBISHI
M66258FP
8192 x 8-BIT LINE MEMORY
* Matters that needs attetion when WCK stops
n cycle
n+1 cycle
n cycle
Disable cycle
WCK tWCK tNWES
WE tDS tDH
tDS tDH
Dn
(n)
(n)
Period for writing data (n) into memory
Period for writing data (n) into memory
WRES = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
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MITSUBISHI
M66258FP
8192 x 8-BIT LINE MEMORY
* Read cycle
n cycle
n+1 cycle
n+2 cycle
Disable cycle
n+3 cycle
n+4 cycle
RCK tRCK tRCKH tRCKL tREH tNRES tNREH tRES tAC RE tODIS tOEN
Qn
(n)
(n+1)
(n+2)
HIGH-Z
(n+3) tOH
(n+4)
RRES = "H"
* Read reset cycle
n-1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
2 cycle
RCK tRCK tNRESH tRESS tRESH tNRESS
RRES
tAC
Qn
(n-1)
(n)
(0)
(0)
(0) tOH
(1)
(2)
RE = "L"
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MITSUBISHI
M66258FP
8192 x 8-BIT LINE MEMORY
VARIABLE LENGTH DELAY BIT
* 1 line (8192 bits) delay Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read cycle to easily make 1 line delay.
0 cycle WCK RCK tRESS tRESH WRES RRES
1 cycle
2 cycle
8190 cycle 8191 cycle
8192 cycle 8193 cycle 8194 cycle (0') (1') (2')
tDS tDH
(0) (1) (2) (8189) (8190) (8191)
tDS tDH
(0') (1') (2') (3')
Dn
8192 cycle Qn
tAC
tOH
(0) (1) (2) (3)
WE, RE = "L"
* n-bit delay bit (Reset at cycles according to the delay length)
0 cycle WCK RCK tRESS tRESH WRES RRES
1 cycle
2 cycle
n-2 cycle
n-1 cycle
n cycle (0')
n+1 cycle (1')
n+2 cycle (2')
n+3 cycle (3')
tRESS tRESH
tDS tDH Dn
(0) (1) (2) (n-3) (n-2) (n-1)
tDS tDH
(0') (1') (2') (3')
m cycle Qn
tAC
tOH
(0) (1) (2) (3)
WE, RE = "L" m3
9
MITSUBISHI
M66258FP
8192 x 8-BIT LINE MEMORY
* n-bit delay 2 (Slides input timings of WRES and RRES at cycles according to the delay length.)
0 cycle WCK RCK tRESS tRESH WRES
1 cycle
2 cycle
n-2 cycle
n-1 cycle
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
tRESS tRESH RRES tDS tDH Dn
(0) (1) (2) (n-2) (n-1) (n)
tDS tDH
(n+1) (n+2) (n+3)
m cycle Qn
tAC
tOH
(0) (1) (2) (3)
WE, RE = "L"
* n-bit delay 3 (Slides address by disabling RE in the period according to the delay length.)
0 cycle WCK RCK tRESS tRESH WRES RRES
1 cycle
2 cycle
n-1 cycle
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
tNREH tRES RE tDS tDH Dn
(0) (1) (2) (n-2) (n-1)
tDS tDH
(n) (n+1) (n+2) (n+3)
m cycle Qn
HIGH-Z
tAC
tOH
(0) (1) (2) (3)
WE, RE = "L" m3
10
MITSUBISHI
M66258FP
8192 x 8-BIT LINE MEMORY
* Reading shortest n-cycle write data "n" (Reading side n-1 cycle starts after the end of writing side n-1 cycle.) When the reading side n-1 cycle starts before the end of the writing side n+1 cycle, output Qn of n cycle is made invalid. In the following diagram, reading operation of n-1 cycle is invalid.
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
WCK
Dn
(n)
(n+1)
(n+2)
(n+3)
n-2 cycle
n-1 cycle
n cycle
RCK
Qn
invalid
(n)
* Reading longest n-cycle write data "n": 1 line delay (When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts.) Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other.
n cycle <1>*
0 cycle <2>*
n cycle <2>*
WCK
Dn
(n-1)<1>*
(n)<1>*
(0)<2>*
(n-1)<2>*
(n)<2>*
n cycle <0>*
0 cycle <1>*
n cycle <1>*
RCK
Qn
(n-1)<0>*
(n)<0>*
(0)<1>*
(n-1)<1>*
(n)<1>*
<0>*, <1>* and <2>* indicate value of lines.
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MITSUBISHI
M66258FP
8192 x 8-BIT LINE MEMORY
APPLICATION EXAMPLE
Sub Scan Resolution Compensation Circuit with Laplacean Filter
M66258 D0 Q0
N n line image data
-
D7 B (n+1) line image data D0
N+K {2N-(A+B)}
X2
Adder
1 line delay
Subtracter
2N-(A+B)
M66258
Q0
D7
Q7
A (n+1) line image data
Adder
1 line delay
Main scan direction
Sub scan direction
A n line
X
B
A+B
(n-1) line
(n+1) line N'=N+K { (N-A) + (N-B) } =N+K { (2N - (A+B) } K: Laplacean coefficient
12
XK
-
Q7 Compensated image data
-
-

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